in connection with
Weimar, Germany, February 18th - 20th, 2009
Shrinking transistor size has increased the available real estate on a die. Combined with the need to keep a lid on power consumption microprocessor vendors increase the number of cores per chip, to improve performance. However, keeping the rising number of available cores busy becomes increasingly difficult. The clock rates per processor are decreasing to keep power consumption low. That leads to the fact that applications that don't take full advantage of additional cores will run slower than they did on older hardware. Even a fully parallelized application may suffer from resource contention created by multiple cores within one processor.
An alternative approach is to add accelerator cards such as General Purpose Graphical Processing Units (GPGPUs) or Field Programmable Gate Arrays (FPGAs). While the accelerator cards open up the possibility of a dramatic performance increase, there is now the challenge of dealing with heterogeneous processors. This introduces an additional layer of software complexity to the multi-core approach.
The purpose of this special session is to address issues relevant to taking full advantage of the additional processing power offered by the multi-core processors and accelerator cards.
Topics include but are not limited to:
Papers submitted for the workshops or special sessions should be submitted directly to the Special Session Chair, Dr. Gabriele Jost (gjost@tacc.utexas.edu). Papers must adhere to the formatting rules of the conference and will undergo the same review process as other papers submitted to the conference.
Authors of accepted papers are expected to register and present the paper at the Conference (for information about PDP 2009 see: http://www.pdp2009.org/ ).